1. Field of the Invention
The present invention relates to a method of manufacturing a silicon semiconductor device, and more particularly to a method of manufacturing a semiconductor device having silicide interconnects.
2. Description of the Related Art
In connecting a conductive pattern formed in the surface of a semiconductor device to another conductive pattern, the surface is once covered with an insulation film a contact hole is formed in the insulation film, and a wiring pattern is formed on the insulation film. This wiring pattern connecting nearby circuits or nodes is called a local interconnect.
A local interconnect for directly connecting a wiring pattern formed on a field oxide film to a diffused region in the substrate surface without forming an interlevel insulation film can dispense with the process of forming an interlevel insulation film and forming a contact hole therein. Such a local interconnect is very suitable for manufacturing fine semiconductor devices and simplifying the manufacture process.
FIGS. 8A to 8D illustrate a method of forming local interconnects using a self-aligned silicide (salicide) technique disclosed in U.S. Pat. No. 4,873,204.
As shown in FIG.8A, locally oxidized field oxide films 101 are formed on the surface of a silicon substrate 100, and active regions 102A and 102B are surrounded and defined by the locally oxidized field oxide films 101. In the active region 102A, a MOSFET is formed which has a source region 103AS, a drain region 103AD, and a gate electrode 104A. In the active region 103B, another MOSFET is formed which has a source region 103BS, a drain region 103BD, and a gate electrode 104B. On both sides of the gate electrodes 104A and 104B, side wall oxide regions or spacers 105A and 105B are formed. The gate electrodes 104A and 104B extend on the active regions and also the locally oxidized field oxide film in the direction perpendicular to the drawing sheet.
A silicon wiring pattern 104C is formed on a locally oxidized field oxide film 101 at the left-most side, and side wall oxide 105c is formed on both sides of the silicon wiring pattern 104C.
A titanium film 106 is deposited over the whole surface of the substrate, and an amorphous silicon film 107 is deposited thereon.
As shown in FIG. 8B, the silicon film 107 is etched to form amorphous silicon patterns 107A and 107B. The silicon pattern 107A extends from the region over the source region 103AS, to the region over the locally oxidized field oxide film 101, and to the region over the silicon wiring pattern 104C. The silicon pattern 107B extends from the region over the drain region 103AD, to the region over the locally oxidized field oxide film 101, and to the region over the source region 103BS.
After the silicon film 107 is patterned, the substrate 100 is heated for annealing.
As shown in FIG. 8C, the titanium film 106 and the silicon surface contacting it are reacted to form a silicide film. The silicon patterns 107A and 107B react with the titanium film 106 to form silicide layers 108A and 108B.
The upper surfaces of the silicon wiring pattern 104C and gate electrodes 104A and 104B are also reacted with the titanium film 106 to form silicide. The surfaces of the source region 103AS, drain region 103AD, source region 103BS, and drain region 103BD are also reacted with the titanium film 106 to form silicide.
As shown in FIG. 8D, an interlevel insulation film 109 is deposited. A contact hole is formed in the interlevel insulation film 109 to expose the surface of the silicide layer 108B. A metal wiring pattern 110 is formed on the interlevel insulation film 109 and covers the exposed surface of the silicide layer 108B in the contact hole.
With the method of forming local interconnects illustrated in FIGS. 8A to 8D, semiconductor active regions in the surface of a silicon substrate and other regions can be connected together without using contact holes. This method is therefore very effective for manufacturing high density semiconductor integrated circuits.
In the method of forming local interconnects, at the process shown in FIG. 8B the regions where the silicon patterns 107A and 107B are formed are covered with a resist pattern, and the exposed silicon film 107 is selectively etched. After etching, the resist pattern used as the etching mask is removed through plasma ashing or through dissolution by acid-containing etchant.
During the removal of resist, the titanium film 106 at the region not covered with the resist pattern is being exposed. Therefore, the exposed titanium film 106 may be oxidized or sputtered by plasma and thinned. Such damages on the titanium film 106 may result in an inability to form a low resistance and good silicide film at the later silicidation process.
Although local interconnects using salicidation techniques are very effective for forming fine semiconductor devices, it can be said that these techniques are still not mature.